inv-schematics/inverter_proto_experimental-cache.lib

EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Transistor_BJT_BCX53
#
DEF Transistor_BJT_BCX53 Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT_BCX53" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-89-3" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS BCX52 BCX53
$FPLIST
 SOT?89*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 100 -100 25 -25 N
P 2 0 1 0 100 100 25 25 N
P 3 0 1 20 25 75 25 -75 25 -75 F
P 5 0 1 0 55 -75 75 -55 35 -35 55 -75 55 -75 F
X B 1 -200 0 200 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# pspice_VSOURCE
#
DEF pspice_VSOURCE V 0 40 Y Y 1 F N
F0 "V" -250 300 50 H V C CNN
F1 "pspice_VSOURCE" 0 0 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 0 200 0 1 0 N
T 0 -320 -10 50 0 0 1 V Normal 0 C C
P 2 0 1 0 -250 -250 -250 150 F
P 3 0 1 0 -300 150 -250 250 -200 150 F
X E1 1 0 300 100 D 50 50 1 1 I
X E2 2 0 -300 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library