Exchanged simple load resistor with transformer.
This commit is contained in:
Marco
parent
174a3e224d
commit
d5d4313f6e
@ -18,6 +18,39 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_Transformer_1P_1S
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#
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DEF Device_Transformer_1P_1S T 0 40 Y N 1 F N
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F0 "T" 0 250 50 H V C CNN
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F1 "Device_Transformer_1P_1S" 0 -300 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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A -100 -150 50 899 1 0 1 0 N -100 -100 -50 -150
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A -100 -150 50 -1 -899 0 1 0 N -50 -150 -100 -199
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A -100 -50 50 899 1 0 1 0 N -100 0 -50 -50
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A -100 -50 50 -1 -899 0 1 0 N -50 -50 -100 -99
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A -100 50 50 899 1 0 1 0 N -100 100 -50 50
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A -100 50 50 -1 -899 0 1 0 N -50 50 -100 1
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A -100 150 50 899 1 0 1 0 N -100 200 -50 150
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A -100 150 50 -1 -899 0 1 0 N -50 150 -100 101
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A 100 -50 50 899 -1799 0 1 0 N 100 0 51 -50
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A 100 -50 50 1799 -899 0 1 0 N 51 -50 100 -99
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A 100 50 50 899 -1799 0 1 0 N 100 100 51 50
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A 100 50 50 1799 -899 0 1 0 N 51 50 100 1
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A 100 150 50 899 -1799 0 1 0 N 100 200 51 150
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A 100 150 50 1799 -899 0 1 0 N 51 150 100 101
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A 101 -150 50 910 -1799 0 1 0 N 101 -100 52 -150
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A 101 -150 50 -912 -1799 0 1 0 N 101 -199 52 -150
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P 2 0 1 0 -25 200 -25 -200 N
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P 2 0 1 0 25 -200 25 200 N
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X AA 1 -400 200 300 R 50 50 1 1 P
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X AB 2 -400 -200 300 R 50 50 1 1 P
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X SA 3 400 -200 300 L 50 50 1 1 P
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X SB 4 400 200 300 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Transistor_BJT_2N2219
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#
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DEF Transistor_BJT_2N2219 Q 0 0 Y N 1 F N
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67
first.sch
67
first.sch
@ -280,12 +280,7 @@ Wire Wire Line
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4750 1750 4750 4800
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Connection ~ 4750 4800
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Wire Wire Line
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4750 4800 6900 4800
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Wire Wire Line
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8700 3300 10150 3300
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Wire Wire Line
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6900 3300 8700 3300
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Connection ~ 8700 3300
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4750 4800 5250 4800
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Wire Wire Line
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8700 3300 8700 5000
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Wire Wire Line
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@ -313,18 +308,58 @@ F 3 "~" H 1900 2450 39 0001 C CNN
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6900 4150 6900 4800
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5250 3850 5250 3300
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Wire Wire Line
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6900 3850 6900 3300
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5250 3300 8700 3300
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Connection ~ 8700 3300
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Wire Wire Line
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8700 3300 10150 3300
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$Comp
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L Device:R R_Load
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U 1 1 60FE4CA7
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P 6900 4000
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F 0 "R_Load" H 6970 4046 50 0000 L CNN
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F 1 "1k" H 6970 3955 50 0000 L CNN
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F 2 "" V 6830 4000 50 0001 C CNN
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F 3 "~" H 6900 4000 50 0001 C CNN
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1 6900 4000
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L Device:Transformer_1P_1S T1
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U 1 1 60F92E27
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P 5650 4050
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F 0 "T1" H 5650 4407 39 0000 C CNN
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F 1 "Transformer_1P_1S" H 5650 4332 39 0000 C CNN
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F 2 "" H 5650 4050 39 0001 C CNN
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F 3 "~" H 5650 4050 39 0001 C CNN
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F 4 "X" H 5650 4050 50 0001 C CNN "Spice_Primitive"
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F 5 "IT" H 5650 4050 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 5650 4050 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "/home/m/projects/electronics/ngspice_models/ideal_transformer.mod" H 5650 4050 50 0001 C CNN "Spice_Lib_File"
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1 5650 4050
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1 0 0 -1
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$EndComp
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Wire Wire Line
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5250 4250 5250 4800
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$Comp
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L Device:R R_Load
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U 1 1 60F942BC
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P 6500 4050
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F 0 "R_Load" H 6570 4096 50 0000 L CNN
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F 1 "1k" H 6570 4005 50 0000 L CNN
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F 2 "" V 6430 4050 50 0001 C CNN
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F 3 "~" H 6500 4050 50 0001 C CNN
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1 6500 4050
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6050 3850 6500 3850
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Wire Wire Line
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6500 3850 6500 3900
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Wire Wire Line
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6500 4200 6500 4250
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Wire Wire Line
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6500 4250 6050 4250
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$Comp
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L power:GND #PWR?
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U 1 1 60F9706B
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P 6500 4250
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F 0 "#PWR?" H 6500 4000 50 0001 C CNN
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F 1 "GND" H 6505 4077 50 0000 C CNN
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F 2 "" H 6500 4250 50 0001 C CNN
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F 3 "" H 6500 4250 50 0001 C CNN
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1 6500 4250
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1 0 0 -1
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$EndComp
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Connection ~ 6500 4250
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$EndSCHEMATC
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330
first.sch-bak
330
first.sch-bak
@ -1,330 +0,0 @@
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 1
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L pspice:VSOURCE Vcc
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U 1 1 6064C406
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P 1050 2200
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F 0 "Vcc" H 1278 2246 50 0000 L CNN
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F 1 "10" H 1278 2155 50 0000 L CNN
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F 2 "" H 1050 2200 50 0001 C CNN
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F 3 "~" H 1050 2200 50 0001 C CNN
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1 1050 2200
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1 0 0 -1
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$EndComp
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$Comp
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L power:GND #PWR?
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U 1 1 6064E58B
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P 1050 6200
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F 0 "#PWR?" H 1050 5950 50 0001 C CNN
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F 1 "GND" H 1055 6027 50 0000 C CNN
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F 2 "" H 1050 6200 50 0001 C CNN
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F 3 "" H 1050 6200 50 0001 C CNN
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1 1050 6200
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1 0 0 -1
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$EndComp
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Wire Wire Line
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1050 1900 1050 1100
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Connection ~ 3350 1550
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Wire Wire Line
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4450 1550 3350 1550
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Wire Wire Line
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4750 1350 4750 1100
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$Comp
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L Transistor_BJT:2N3905 Q12
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U 1 1 60F7E2F2
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P 4650 1550
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F 0 "Q12" H 4840 1504 50 0000 L CNN
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F 1 "2N3905" H 4840 1595 50 0000 L CNN
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F 2 "Package_TO_SOT_THT:TO-92_Inline" H 4850 1475 50 0001 L CIN
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F 3 "https://www.nteinc.com/specs/original/2N3905_06.pdf" H 4650 1550 50 0001 L CNN
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F 4 "Q" H 4650 1550 50 0001 C CNN "Spice_Primitive"
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F 5 "bdx54c" H 4650 1550 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 4650 1550 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "bdx54c.lib" H 4650 1550 50 0001 C CNN "Spice_Lib_File"
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1 4650 1550
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1 0 0 1
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$EndComp
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Wire Wire Line
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3350 1250 3350 1100
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$Comp
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L Device:R Rpu1
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U 1 1 60F79F09
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P 3350 1400
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F 0 "Rpu1" H 3420 1446 50 0000 L CNN
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F 1 "10k" H 3420 1355 50 0000 L CNN
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F 2 "" V 3280 1400 50 0001 C CNN
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F 3 "~" H 3350 1400 50 0001 C CNN
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1 3350 1400
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1 0 0 -1
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$EndComp
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Wire Wire Line
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1050 1100 3350 1100
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Wire Wire Line
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1900 1900 3050 1900
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Connection ~ 3350 1100
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Wire Wire Line
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3350 1100 4750 1100
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Wire Wire Line
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3350 1550 3350 1700
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Connection ~ 1050 2950
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Wire Wire Line
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1900 1900 1900 2150
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Wire Wire Line
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1050 2950 1900 2950
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Wire Wire Line
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1900 2750 1900 2950
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Connection ~ 1900 2950
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Wire Wire Line
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1900 2950 3350 2950
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Wire Wire Line
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3350 2100 3350 2950
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Text GLabel 1900 1900 0 50 Input ~ 0
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V11
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$Comp
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L Transistor_BJT:2N2219 Q11
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U 1 1 60F73E70
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P 3250 1900
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F 0 "Q11" H 3440 1946 50 0000 L CNN
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F 1 "2N2219" H 3440 1855 50 0000 L CNN
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F 2 "Package_TO_SOT_THT:TO-39-3" H 3450 1825 50 0001 L CIN
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F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 3250 1900 50 0001 L CNN
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F 4 "Q" H 3250 1900 50 0001 C CNN "Spice_Primitive"
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F 5 "2N2219" H 3250 1900 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 3250 1900 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "2N2219.LIB" H 3250 1900 50 0001 C CNN "Spice_Lib_File"
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||||
1 3250 1900
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1 0 0 -1
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$EndComp
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Wire Wire Line
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1050 2950 1050 6200
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Wire Wire Line
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1050 2600 1050 2950
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Wire Wire Line
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1050 2500 1050 2950
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Connection ~ 1050 6200
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Wire Wire Line
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8700 5400 8700 6200
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Wire Wire Line
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7250 5200 7250 5350
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Text GLabel 7250 5200 0 50 Input ~ 0
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V22
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Wire Wire Line
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7250 5200 8400 5200
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$Comp
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L Transistor_BJT:2N2219 Q4
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U 1 1 60FB5A31
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P 8600 5200
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F 0 "Q4" H 8790 5246 50 0000 L CNN
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F 1 "2N2219" H 8790 5155 50 0000 L CNN
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||||
F 2 "Package_TO_SOT_THT:TO-39-3" H 8800 5125 50 0001 L CIN
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F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 8600 5200 50 0001 L CNN
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||||
F 4 "Q" H 8600 5200 50 0001 C CNN "Spice_Primitive"
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F 5 "2N2219" H 8600 5200 50 0001 C CNN "Spice_Model"
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||||
F 6 "Y" H 8600 5200 50 0001 C CNN "Spice_Netlist_Enabled"
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||||
F 7 "2N2219.LIB" H 8600 5200 50 0001 C CNN "Spice_Lib_File"
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||||
1 8600 5200
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||||
1 0 0 -1
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||||
$EndComp
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||||
Wire Wire Line
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7250 6200 8700 6200
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Connection ~ 7250 6200
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Wire Wire Line
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7250 6200 7250 5950
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Wire Wire Line
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1050 6200 1900 6200
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Connection ~ 1900 6200
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Wire Wire Line
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1900 6200 1900 5950
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Connection ~ 4750 1100
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Wire Wire Line
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4750 1100 8700 1100
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Wire Wire Line
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10150 1350 10150 1100
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Wire Wire Line
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8700 1250 8700 1100
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Connection ~ 8700 1100
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Wire Wire Line
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8700 1100 10150 1100
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Wire Wire Line
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9850 1550 8700 1550
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$Comp
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L Transistor_BJT:2N3905 Q22
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U 1 1 60F9BAB5
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P 10050 1550
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F 0 "Q22" H 10240 1504 50 0000 L CNN
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F 1 "2N3905" H 10240 1595 50 0000 L CNN
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F 2 "Package_TO_SOT_THT:TO-92_Inline" H 10250 1475 50 0001 L CIN
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F 3 "https://www.nteinc.com/specs/original/2N3905_06.pdf" H 10050 1550 50 0001 L CNN
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F 4 "Q" H 10050 1550 50 0001 C CNN "Spice_Primitive"
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F 5 "bdx54c" H 10050 1550 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 10050 1550 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "bdx54c.lib" H 10050 1550 50 0001 C CNN "Spice_Lib_File"
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1 10050 1550
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1 0 0 1
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$EndComp
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||||
$Comp
|
||||
L Device:R Rpu2
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U 1 1 60F9BABC
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P 8700 1400
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F 0 "Rpu2" H 8770 1446 50 0000 L CNN
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F 1 "10k" H 8770 1355 50 0000 L CNN
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F 2 "" V 8630 1400 50 0001 C CNN
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F 3 "~" H 8700 1400 50 0001 C CNN
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1 8700 1400
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1 0 0 -1
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$EndComp
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$Comp
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L Transistor_BJT:2N2219 Q21
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U 1 1 60F9BAC6
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P 8600 1900
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F 0 "Q21" H 8790 1946 50 0000 L CNN
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F 1 "2N2219" H 8790 1855 50 0000 L CNN
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F 2 "Package_TO_SOT_THT:TO-39-3" H 8800 1825 50 0001 L CIN
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F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 8600 1900 50 0001 L CNN
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F 4 "Q" H 8600 1900 50 0001 C CNN "Spice_Primitive"
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F 5 "2N2219" H 8600 1900 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 8600 1900 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "2N2219.LIB" H 8600 1900 50 0001 C CNN "Spice_Lib_File"
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1 8600 1900
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1 0 0 -1
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$EndComp
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Wire Wire Line
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7250 1900 8400 1900
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Connection ~ 8700 1550
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Wire Wire Line
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8700 1550 8700 1700
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Wire Wire Line
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7250 1900 7250 2150
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Wire Wire Line
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7250 2750 7250 2950
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Wire Wire Line
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7250 2950 8700 2950
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Connection ~ 7250 2950
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Connection ~ 3350 2950
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Wire Wire Line
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3350 2950 7250 2950
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Wire Wire Line
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8700 2100 8700 2950
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Text GLabel 7250 1900 0 50 Input ~ 0
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V12
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Wire Wire Line
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1900 6200 3350 6200
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Connection ~ 3350 6200
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Wire Wire Line
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3350 5500 3350 6200
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Wire Wire Line
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1900 5300 1900 5350
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Text GLabel 1900 5300 0 50 Input ~ 0
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V21
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Wire Wire Line
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1900 5300 3050 5300
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$Comp
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L Transistor_BJT:2N2219 Q3
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U 1 1 60FABDE3
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P 3250 5300
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F 0 "Q3" H 3440 5346 50 0000 L CNN
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F 1 "2N2219" H 3440 5255 50 0000 L CNN
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F 2 "Package_TO_SOT_THT:TO-39-3" H 3450 5225 50 0001 L CIN
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F 3 "http://www.onsemi.com/pub_link/Collateral/2N2219-D.PDF" H 3250 5300 50 0001 L CNN
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F 4 "Q" H 3250 5300 50 0001 C CNN "Spice_Primitive"
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F 5 "2N2219" H 3250 5300 50 0001 C CNN "Spice_Model"
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F 6 "Y" H 3250 5300 50 0001 C CNN "Spice_Netlist_Enabled"
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F 7 "2N2219.LIB" H 3250 5300 50 0001 C CNN "Spice_Lib_File"
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1 3250 5300
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1 0 0 -1
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$EndComp
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Text Notes 600 7550 0 50 ~ 0
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.tran 1n 1m
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$Comp
|
||||
L pspice:VSOURCE V21
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U 1 1 60FABDEA
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P 1900 5650
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||||
F 0 "V21" H 2128 5696 39 0000 L CNN
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||||
F 1 "PULSE(0 5 400u 1n 1n 200u 0 0)" H 2128 5605 39 0000 L CNN
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||||
F 2 "" H 1900 5650 39 0001 C CNN
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||||
F 3 "~" H 1900 5650 39 0001 C CNN
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||||
1 1900 5650
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||||
1 0 0 -1
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$EndComp
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||||
$Comp
|
||||
L pspice:VSOURCE V22
|
||||
U 1 1 60FB5A38
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||||
P 7250 5650
|
||||
F 0 "V22" H 7478 5696 39 0000 L CNN
|
||||
F 1 "PULSE(0 5 100u 1n 1n 200u 0 0)" H 7478 5605 39 0000 L CNN
|
||||
F 2 "" H 7250 5650 39 0001 C CNN
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||||
F 3 "~" H 7250 5650 39 0001 C CNN
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||||
1 7250 5650
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||||
1 0 0 -1
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||||
$EndComp
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||||
Wire Wire Line
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||||
3350 6200 7250 6200
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||||
Wire Wire Line
|
||||
3350 4800 3350 5100
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||||
Wire Wire Line
|
||||
3350 4800 4750 4800
|
||||
Wire Wire Line
|
||||
4750 1750 4750 4800
|
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Connection ~ 4750 4800
|
||||
Wire Wire Line
|
||||
4750 4800 6900 4800
|
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Wire Wire Line
|
||||
8700 3300 10150 3300
|
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Wire Wire Line
|
||||
6900 3300 8700 3300
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Connection ~ 8700 3300
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||||
Wire Wire Line
|
||||
8700 3300 8700 5000
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||||
Wire Wire Line
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||||
10150 1750 10150 3300
|
||||
$Comp
|
||||
L pspice:VSOURCE V12
|
||||
U 1 1 60FA5ACD
|
||||
P 7250 2450
|
||||
F 0 "V12" H 7478 2496 39 0000 L CNN
|
||||
F 1 "PULSE(0 5 400u 1n 1n 200u 0 0)" H 7478 2405 39 0000 L CNN
|
||||
F 2 "" H 7250 2450 39 0001 C CNN
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||||
F 3 "~" H 7250 2450 39 0001 C CNN
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||||
1 7250 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L pspice:VSOURCE V11
|
||||
U 1 1 6064E251
|
||||
P 1900 2450
|
||||
F 0 "V11" H 2128 2496 39 0000 L CNN
|
||||
F 1 "PULSE(0 5 100u 1n 1n 200u 0 0)" H 2128 2405 39 0000 L CNN
|
||||
F 2 "" H 1900 2450 39 0001 C CNN
|
||||
F 3 "~" H 1900 2450 39 0001 C CNN
|
||||
1 1900 2450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
6900 4150 6900 4800
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3300
|
||||
$Comp
|
||||
L Device:R R_Load
|
||||
U 1 1 60FE4CA7
|
||||
P 6900 4000
|
||||
F 0 "R_Load" H 6970 4046 50 0000 L CNN
|
||||
F 1 "1k" H 6970 3955 50 0000 L CNN
|
||||
F 2 "" V 6830 4000 50 0001 C CNN
|
||||
F 3 "~" H 6900 4000 50 0001 C CNN
|
||||
1 6900 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
Loading…
Reference in New Issue
Block a user