marco/inv-sw-32u4
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1. Remove ISR for Timer0 Compare Unit.

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2. Change chip select but keep 1kHz frequency of Timer1 PWM.
This commit is contained in:
Marco 2022-05-30 06:10:18 +02:00
parent e595fcc78f
commit 927276afb5
1 changed files with 10 additions and 17 deletions
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27
src/timer.c
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@ -8,12 +8,18 @@
void initPwmTimer1(void)
{
/*
* We are using Timer 1 Compare Match Unit B.
* OC1B is on Pin PB6. Let's make it an output.
*/
DDRB |= (1 << DDB6);
/* Enable Fast PWM with TOP in OCR1A */
TCCR1A |= (1 << WGM11) | (1 << WGM10);
TCCR1B |= (1 << WGM13) | (1 << WGM12);
/* Clock prescaler of 8 */
TCCR1B |= (1 << CS11);
/* Clock prescaler of 64 */
TCCR1B |= (1 << CS11) | (1 << CS10);
/* Set OC1B on compare match, clear OC1B at TOP */
TCCR1A |= (1 << COM1B1);
@ -22,10 +28,10 @@ void initPwmTimer1(void)
TIMSK1 |= (1 << OCIE1B);
/* TOP value */
OCR1A = 1000;
OCR1A = 125;
/* Compare Match with OCR1B */
OCR1B = 10;
OCR1B = 62;
}
void initCtcTimer0(void)
@ -62,16 +68,3 @@ void initOverflowTimer1(void)
TCCR1B |= (1<<CS11);
TIMSK1 |= (1<<TOIE1);
}
volatile double sin_op = 0.0;
volatile uint8_t wait_cnt = 0;
ISR(TIMER0_COMPA_vect)
{
if (wait_cnt > 0) {
printf("%.2lf\n\r", sin(sin_op));
sin_op = ((sin_op + 0.01) > 2*M_PI) ? 0.0 : sin_op + .01;
wait_cnt = 0;
}
wait_cnt++;
}