f5fe6fe5cc
* add device one * fix layouts * add other layouts * column fixes, device id changes * layouts cleanup, add readme * add info.json, fix readme * add template readme * add smaller image * fix image links, address requested changes * Apply suggestions from code review * Update keyboards/device_one/keymaps/ansi_split_backspace/keymap.c * add akegata vendor folder * Apply suggestions from code review
188 lines
6.7 KiB
C
188 lines
6.7 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F0xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 3...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F0xx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_HSI14_ENABLED TRUE
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#define STM32_HSI48_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
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#define STM32_PREDIV_VALUE 1
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#define STM32_PLLMUL_VALUE 12
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
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#define STM32_USBSW STM32_USBSW_HSI48
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#define STM32_CECSW STM32_CECSW_HSI
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#define STM32_I2C1SW STM32_I2C1SW_HSI
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#define STM32_USART1SW STM32_USART1SW_PCLK
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
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#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
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#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
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#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
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#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
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#define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_TIM1_IRQ_PRIORITY 2
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#define STM32_GPT_TIM2_IRQ_PRIORITY 2
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#define STM32_GPT_TIM3_IRQ_PRIORITY 2
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#define STM32_GPT_TIM14_IRQ_PRIORITY 2
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 3
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* I2S driver system settings.
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*/
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#define STM32_I2S_USE_SPI1 FALSE
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#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
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STM32_I2S_MODE_RX)
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#define STM32_I2S_SPI1_IRQ_PRIORITY 2
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#define STM32_I2S_SPI1_DMA_PRIORITY 1
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#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 3
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#define STM32_ICU_TIM2_IRQ_PRIORITY 3
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#define STM32_ICU_TIM3_IRQ_PRIORITY 3
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY 3
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#define STM32_PWM_TIM2_IRQ_PRIORITY 3
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#define STM32_PWM_TIM3_IRQ_PRIORITY 3
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USART1_PRIORITY 3
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#define STM32_SERIAL_USART2_PRIORITY 3
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 2
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#define STM32_ST_USE_TIMER 2
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USART1_IRQ_PRIORITY 3
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_USB1 TRUE
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#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
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#define STM32_USB_USB1_LP_IRQ_PRIORITY 3
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#endif /* MCUCONF_H */
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