marco/inv-schematics
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Adding .gitignore.

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Minor modifications of schematic.
This commit is contained in:
Marco 2021-07-21 20:17:29 +02:00
parent d5d4313f6e
commit c35092d47f
2 changed files with 82 additions and 26 deletions
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1
.gitignore vendored Normal file
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@ -0,0 +1 @@
first.sch-bak

107
first.sch
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@ -18,7 +18,7 @@ L pspice:VSOURCE Vcc
U 1 1 6064C406
P 1050 2200
F 0 "Vcc" H 1278 2246 50 0000 L CNN
F 1 "10" H 1278 2155 50 0000 L CNN
F 1 "20" H 1278 2155 50 0000 L CNN
F 2 "" H 1050 2200 50 0001 C CNN
F 3 "~" H 1050 2200 50 0001 C CNN
1 1050 2200
@ -64,7 +64,7 @@ L Device:R Rpu1
U 1 1 60F79F09
P 3350 1400
F 0 "Rpu1" H 3420 1446 50 0000 L CNN
F 1 "10k" H 3420 1355 50 0000 L CNN
F 1 "100k" H 3420 1355 50 0000 L CNN
F 2 "" V 3280 1400 50 0001 C CNN
F 3 "~" H 3350 1400 50 0001 C CNN
1 3350 1400
@ -73,7 +73,7 @@ $EndComp
Wire Wire Line
1050 1100 3350 1100
Wire Wire Line
1900 1900 3050 1900
1900 1900 2200 1900
Connection ~ 3350 1100
Wire Wire Line
3350 1100 4750 1100
@ -87,10 +87,6 @@ Wire Wire Line
Wire Wire Line
1900 2750 1900 2950
Connection ~ 1900 2950
Wire Wire Line
1900 2950 3350 2950
Wire Wire Line
3350 2100 3350 2950
Text GLabel 1900 1900 0 50 Input ~ 0
V11
$Comp
@ -122,7 +118,7 @@ Wire Wire Line
Text GLabel 7250 5200 0 50 Input ~ 0
V22
Wire Wire Line
7250 5200 8400 5200
7250 5200 7650 5200
$Comp
L Transistor_BJT:2N2219 Q4
U 1 1 60FB5A31
@ -180,7 +176,7 @@ L Device:R Rpu2
U 1 1 60F9BABC
P 8700 1400
F 0 "Rpu2" H 8770 1446 50 0000 L CNN
F 1 "10k" H 8770 1355 50 0000 L CNN
F 1 "100k" H 8770 1355 50 0000 L CNN
F 2 "" V 8630 1400 50 0001 C CNN
F 3 "~" H 8700 1400 50 0001 C CNN
1 8700 1400
@ -201,8 +197,6 @@ F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 8600 1900 50 000
1 8600 1900
1 0 0 -1
$EndComp
Wire Wire Line
7250 1900 8400 1900
Connection ~ 8700 1550
Wire Wire Line
8700 1550 8700 1700
@ -213,9 +207,6 @@ Wire Wire Line
Wire Wire Line
7250 2950 8700 2950
Connection ~ 7250 2950
Connection ~ 3350 2950
Wire Wire Line
3350 2950 7250 2950
Wire Wire Line
8700 2100 8700 2950
Text GLabel 7250 1900 0 50 Input ~ 0
@ -230,7 +221,7 @@ Wire Wire Line
Text GLabel 1900 5300 0 50 Input ~ 0
V21
Wire Wire Line
1900 5300 3050 5300
1900 5300 2250 5300
$Comp
L Transistor_BJT:2N2219 Q3
U 1 1 60FABDE3
@ -247,13 +238,13 @@ F 7 "/home/m/projects/electronics/ngspice_models/2N2219.LIB" H 3250 5300 50 000
1 0 0 -1
$EndComp
Text Notes 600 7550 0 50 ~ 0
.tran 1n 1m
.tran 50p 250u
$Comp
L pspice:VSOURCE V21
U 1 1 60FABDEA
P 1900 5650
F 0 "V21" H 2128 5696 39 0000 L CNN
F 1 "PULSE(0 5 400u 1n 1n 200u 0 0)" H 2128 5605 39 0000 L CNN
F 1 "PULSE(0 5 120u 1n 1n 100u 0 0)" H 2128 5605 39 0000 L CNN
F 2 "" H 1900 5650 39 0001 C CNN
F 3 "~" H 1900 5650 39 0001 C CNN
1 1900 5650
@ -264,7 +255,7 @@ L pspice:VSOURCE V22
U 1 1 60FB5A38
P 7250 5650
F 0 "V22" H 7478 5696 39 0000 L CNN
F 1 "PULSE(0 5 100u 1n 1n 200u 0 0)" H 7478 5605 39 0000 L CNN
F 1 "PULSE(0 5 10u 1n 1n 100u 0 0)" H 7478 5605 39 0000 L CNN
F 2 "" H 7250 5650 39 0001 C CNN
F 3 "~" H 7250 5650 39 0001 C CNN
1 7250 5650
@ -276,21 +267,17 @@ Wire Wire Line
3350 4800 3350 5100
Wire Wire Line
3350 4800 4750 4800
Wire Wire Line
4750 1750 4750 4800
Connection ~ 4750 4800
Wire Wire Line
4750 4800 5250 4800
Wire Wire Line
8700 3300 8700 5000
Wire Wire Line
10150 1750 10150 3300
$Comp
L pspice:VSOURCE V12
U 1 1 60FA5ACD
P 7250 2450
F 0 "V12" H 7478 2496 39 0000 L CNN
F 1 "PULSE(0 5 400u 1n 1n 200u 0 0)" H 7478 2405 39 0000 L CNN
F 1 "PULSE(0 5 120u 1n 1n 100u 0 0)" H 7478 2405 39 0000 L CNN
F 2 "" H 7250 2450 39 0001 C CNN
F 3 "~" H 7250 2450 39 0001 C CNN
1 7250 2450
@ -301,7 +288,7 @@ L pspice:VSOURCE V11
U 1 1 6064E251
P 1900 2450
F 0 "V11" H 2128 2496 39 0000 L CNN
F 1 "PULSE(0 5 100u 1n 1n 200u 0 0)" H 2128 2405 39 0000 L CNN
F 1 "PULSE(0 5 10u 1n 1n 100u 0 0)" H 2128 2405 39 0000 L CNN
F 2 "" H 1900 2450 39 0001 C CNN
F 3 "~" H 1900 2450 39 0001 C CNN
1 1900 2450
@ -326,6 +313,7 @@ F 4 "X" H 5650 4050 50 0001 C CNN "Spice_Primitive"
F 5 "IT" H 5650 4050 50 0001 C CNN "Spice_Model"
F 6 "Y" H 5650 4050 50 0001 C CNN "Spice_Netlist_Enabled"
F 7 "/home/m/projects/electronics/ngspice_models/ideal_transformer.mod" H 5650 4050 50 0001 C CNN "Spice_Lib_File"
F 8 "1 2 4 3" H 5650 4050 50 0001 C CNN "Spice_Node_Sequence"
1 5650 4050
1 0 0 -1
$EndComp
@ -342,8 +330,6 @@ F 3 "~" H 6500 4050 50 0001 C CNN
1 6500 4050
1 0 0 -1
$EndComp
Wire Wire Line
6050 3850 6500 3850
Wire Wire Line
6500 3850 6500 3900
Wire Wire Line
@ -362,4 +348,73 @@ F 3 "" H 6500 4250 50 0001 C CNN
1 0 0 -1
$EndComp
Connection ~ 6500 4250
Text GLabel 6500 3850 2 50 Input ~ 0
V_load
Wire Wire Line
6050 3850 6500 3850
Wire Wire Line
1900 2950 3350 2950
Connection ~ 3350 2950
Wire Wire Line
3350 2950 7250 2950
Wire Wire Line
10150 1750 10150 3300
Wire Wire Line
3350 2100 3350 2950
$Comp
L Device:R R_b11
U 1 1 60FA7473
P 2350 1900
F 0 "R_b11" V 2143 1900 50 0000 C CNN
F 1 "100" V 2234 1900 50 0000 C CNN
F 2 "" V 2280 1900 50 0001 C CNN
F 3 "~" H 2350 1900 50 0001 C CNN
1 2350 1900
0 1 1 0
$EndComp
Wire Wire Line
2500 1900 3050 1900
$Comp
L Device:R R_b12
U 1 1 60FAC87E
P 7750 1900
F 0 "R_b12" V 7543 1900 50 0000 C CNN
F 1 "100" V 7634 1900 50 0000 C CNN
F 2 "" V 7680 1900 50 0001 C CNN
F 3 "~" H 7750 1900 50 0001 C CNN
1 7750 1900
0 1 1 0
$EndComp
Wire Wire Line
7250 1900 7600 1900
Wire Wire Line
7900 1900 8400 1900
$Comp
L Device:R R_b22
U 1 1 60FB05BB
P 7800 5200
F 0 "R_b22" V 7593 5200 50 0000 C CNN
F 1 "100" V 7684 5200 50 0000 C CNN
F 2 "" V 7730 5200 50 0001 C CNN
F 3 "~" H 7800 5200 50 0001 C CNN
1 7800 5200
0 1 1 0
$EndComp
$Comp
L Device:R R_b21
U 1 1 60FB24E9
P 2400 5300
F 0 "R_b21" V 2193 5300 50 0000 C CNN
F 1 "100" V 2284 5300 50 0000 C CNN
F 2 "" V 2330 5300 50 0001 C CNN
F 3 "~" H 2400 5300 50 0001 C CNN
1 2400 5300
0 1 1 0
$EndComp
Wire Wire Line
2550 5300 3050 5300
Wire Wire Line
7950 5200 8400 5200
Wire Wire Line
4750 1750 4750 4800
$EndSCHEMATC